Freescale Semiconductor /MKW21Z4 /XCVR_CTRL_REGS /DMA_CTRL

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Interpret as DMA_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0000)DMA_PAGE 0 (0)SINGLE_REQ_MODE 0 (0)BYPASS_DMA_SYNC 0 (DMA_TRIGGERRED)DMA_TRIGGERRED 0 (0)DMA_TIMED_OUT 0DMA_TIMEOUT

DMA_PAGE=0000, DMA_TIMED_OUT=0, BYPASS_DMA_SYNC=0, SINGLE_REQ_MODE=0

Description

TRANSCEIVER DMA CONTROL

Fields

DMA_PAGE

Transceiver DMA Page Selector

0 (0000): DMA Idle

1 (0001): RX_DIG I and Q

2 (0010): RX_DIG I Only

3 (0011): RX_DIG Q Only

4 (0100): RAW ADC I and Q

5 (0101): RAW ADC I Only

6 (0110): RAW ADC Q only

7 (0111): DC Estimator I and Q

8 (1000): DC Estimator I Only

9 (1001): DC Estimator Q only

10 (1010): RX_DIG Phase Output

11 (1011): Demodulator Hard Decision

12 (1100): Demodulator Soft Decision

13 (1101): Demodulator Data Output

14 (1110): Demodulator CFO Phase Output

SINGLE_REQ_MODE

DMA Single Request Mode

0 (0): Disable Single Request Mode. The transceiver will assert ipd_req_radio_rx whenever it has a new sample ready for transfer.

1 (1): Enable Single Request Mode. A single initial request by the transceiver will transfer the entire DMA block of data

BYPASS_DMA_SYNC

Bypass External DMA Synchronization

0 (0): Don’t Bypass External Synchronization. Use this setting if SINGLE_REQ_MODE=1.

1 (1): Bypass External Synchronization. This setting is mandatory if SINGLE_REQ_MODE=0.

DMA_TRIGGERRED

DMA TRIGGERRED

DMA_TIMED_OUT

DMA Transfer Timed Out

0 (0): A DMA timeout has not occurred

1 (1): A DMA timeout has occurred in Single Request Mode since the last time this bit was cleared

DMA_TIMEOUT

DMA Timeout

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